1. What is callback ?
2. What is factory pattern ?
3. Explain the difference between data types logic and reg and wire
4. What is the need of clocking blocks ?
5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
6. Explain Event regions in SV.
7. What are the types of coverages available in SV ?
8. What is OOPS?
9. What is inheritance and polymorphism?
10. What is the need of virtual interfaces ?
11. Explain about the virtual task and methods .
12. What is the use of the abstract class?
13. What is the difference between mailbox and queue?
14. What data structure you used to build scoreboard
15. What are the advantages of linkedlist over the queue ?
16. How parallel case and full cases problems are avoided in SV
17. What is the difference between pure function and cordinary function ?
18. What is the difference between $random and $urandom?
19. What is scope randomization
20. List the predefined randomization methods.
21. What is the dfference between always_combo and always@(*)?
22. What is the use of packagess?
23. What is the use of $cast?
24. How to call the task which is defined in parent object into derived class ?
25. What is the difference between rand and randc?
26. What is $root?
27. What is $unit?
28. What are bi-directional constraints?
29. What is solve...before constraint ?
30. Without using randomize method or rand,generate an array of unique values?
31. Explain about pass by ref and pass by value?
32. What is the difference between bit[7:0] sig_1; and byte sig_2;
33. What is the difference between program block and module ?
34. What is final block ?
35. How to implement always block logic in program block ?
36. What is the difference between fork/joins, fork/join_none fork/join_any ?
37. What is the use of modports ?
38. Write a clock generator without using always block.
39. What is forward referencing and how to avoid this problem?
40. What is circular dependency and how to avoid this problem ?
41. What is cross coverage ?
42. Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them
43. How to kill a process in fork/join?
44. Difference between Associative array and Dynamic array ?
45. Difference b/w Procedural and Concarent Assertions?
46. What are the advantages of SystemVerilog DPI?
47. How to randomize dynamic arrays of objects?
48. What is randsequence and what is its use?
49. What is bin?
50. Why always block is not allowed in program block?
51. Which is best to use to model transaction? Struct or class ?
52. How SV is more random stable then Verilog?
53. Difference between assert and expect statements?
54. How to add a new processs with out disturbing the random number generator state ?
55. What is the need of alias in SV?
56. What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?
57. How different is the implementation of a struct and union in SV.
58. What is "this"?
59. What is tagged union ?
60. What is "scope resolution operator"?
61. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?
62. What is the difference between
view source
print?
1.logic data_1;
2.var logic data_2;
3.wire logic data_3j;
4.bit data_4;
5.var bit data_5;
63. What is the difference between bits and logic?
64. Write a Statemechine in SV styles.
65. What is the difference between $rose and posedge?
66. What is advantage of program block over clockcblock w.r.t race condition?
67. How to avoid the race condition between programblock ?
68. What is the difference between assumes and assert?
69. What is coverage driven verification?
70. What is layered architecture ?
71. What are the simulation phases in your verification environment?
72. How to pick a element which is in queue from random index?
73. What data structure is used to store data in your environment and why ?
74. What is casting? Explain about the various types of casting available in SV.
75. How to import all the items declared inside a package ?
76. Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?
77. What is streaming operator and what is its use?
78. What are void functions ?
79. How to make sure that a function argument passed has ref is not changed by the function?
80. What is the use of "extern"?
81. What is the difference between initial block and final block?
82. How to check weather a handles is holding object or not ?
83. How to disable multiple threads which are spawned by fork...join
84 Why cannot initial statement be synthesizeable ?
85 Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?
86a What is the difference between blocking and nonblocking assignments ?
86 What is the difference between wire and reg data type ?
87 Write code for async reset D-Flip-Flop.
88 Write code for 2:1 MUX using different coding methods.
89 Write code for a parallel encoder and a priority encoder.
90 What is the difference between === and == ?
91 What is defparam used for ?
92 What is the difference between unary and logical operators ?
93 What is the difference between tasks and functions ?
94 What is the difference between transport and inertial delays ?
95 What is the difference between casex and case statements ?
96 What is the difference between $monitor and $display ?
97 What is the difference between compiled, interpreted, event based and cycle based simulators ?
98 What is code coverage and what are the different types of code coverage that one does ?
99 How will you handle multiple interfaces in UVM.
100 Explain APB and AHB using state machine
101 Explain Polymorphism and Inheritance using examples.
102When to use blocking and when to use non-blocking assignments.
103How do you control sequences in UVM {through testcase}.
1. Explain NAND flash operation
2. Diff btwn task & function
3. Types of arrays.
4. Advantage of dynamic array over associative array
5. Can you declare everything as associative array?
6. Explain packed and un packed array
7. Types of sequences
8. Explain ahb signals
9. Explain in details split and retry in hresp
10. Diff btwn @posedge and $rose
11. Uvm how driver and sequencer interact
12. How data passes from layer to layer in uvm
13. Diff btwn reg n wire
14. Diff between blocking n non blocking
15. Draw waveform for the code
Module ex;
Input [2:0] a;
Begin
a<= 3’b000;
a<=#5 3’b010;
a = #10 3’b101;
a<= #20 3’b111;
end
endmodule
16. How do you pass an array to a function.
17. About PREADY signal: is there a PREADY input to the slave
18. Without constraint, how will u generate random number between the range ‘x’ and ‘y’.
19. How to reduce the number of clock cycles taken for a transfer in APB/AHB protocol.. Eg: suppose a transfer takes 4 clock cycles, how can we make it in 3.
20. What does an ISR do. Suppose you have to write an isr, what all things you will write in that handler.
21. SIMULATOR related: when we compile any code, we give a filelist and the compiler compiles all the files in the list. Suppose some of the files is calling another file(`include option), then how will we compile that included file/directory
22. Basic verification approach: how will you verify an IP, in an SOC environment… how will you build the VC(approach).
23. Why sv over Verilog( explain properties of oops)
24. What is inheritance and polymorphism explain with example
25. Why/explain casting is used in terms of class and handles
26. Data types in sv
27. Randomization?
28. Cyclc randomization
29. How probability distribution is achived
Ex. 50% of time a =0
25% of time a = ( 1 - 1000)
25% of time a = (1001 – 2^32 - 1) how do you achieve this
30. Explain wait, randcase
31. Explain semaphore and mailboxes?
32. Mailboxes how does it work
33. Diff btwn mailbox and Que
34. Explain addr phase and data phase in AHB
35. Explain uvm flow
36. As soon as you get the spec how do you start verification
37. Why phases are required
2. What is factory pattern ?
3. Explain the difference between data types logic and reg and wire
4. What is the need of clocking blocks ?
5. What are the ways to avoid race condition between testbench and RTL using SystemVerilog?
6. Explain Event regions in SV.
7. What are the types of coverages available in SV ?
8. What is OOPS?
9. What is inheritance and polymorphism?
10. What is the need of virtual interfaces ?
11. Explain about the virtual task and methods .
12. What is the use of the abstract class?
13. What is the difference between mailbox and queue?
14. What data structure you used to build scoreboard
15. What are the advantages of linkedlist over the queue ?
16. How parallel case and full cases problems are avoided in SV
17. What is the difference between pure function and cordinary function ?
18. What is the difference between $random and $urandom?
19. What is scope randomization
20. List the predefined randomization methods.
21. What is the dfference between always_combo and always@(*)?
22. What is the use of packagess?
23. What is the use of $cast?
24. How to call the task which is defined in parent object into derived class ?
25. What is the difference between rand and randc?
26. What is $root?
27. What is $unit?
28. What are bi-directional constraints?
29. What is solve...before constraint ?
30. Without using randomize method or rand,generate an array of unique values?
31. Explain about pass by ref and pass by value?
32. What is the difference between bit[7:0] sig_1; and byte sig_2;
33. What is the difference between program block and module ?
34. What is final block ?
35. How to implement always block logic in program block ?
36. What is the difference between fork/joins, fork/join_none fork/join_any ?
37. What is the use of modports ?
38. Write a clock generator without using always block.
39. What is forward referencing and how to avoid this problem?
40. What is circular dependency and how to avoid this problem ?
41. What is cross coverage ?
42. Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them
43. How to kill a process in fork/join?
44. Difference between Associative array and Dynamic array ?
45. Difference b/w Procedural and Concarent Assertions?
46. What are the advantages of SystemVerilog DPI?
47. How to randomize dynamic arrays of objects?
48. What is randsequence and what is its use?
49. What is bin?
50. Why always block is not allowed in program block?
51. Which is best to use to model transaction? Struct or class ?
52. How SV is more random stable then Verilog?
53. Difference between assert and expect statements?
54. How to add a new processs with out disturbing the random number generator state ?
55. What is the need of alias in SV?
56. What is the need to implement explicitly a copy() method inside a transaction , when we can simple assign one object to other ?
57. How different is the implementation of a struct and union in SV.
58. What is "this"?
59. What is tagged union ?
60. What is "scope resolution operator"?
61. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros?
62. What is the difference between
view source
print?
1.logic data_1;
2.var logic data_2;
3.wire logic data_3j;
4.bit data_4;
5.var bit data_5;
63. What is the difference between bits and logic?
64. Write a Statemechine in SV styles.
65. What is the difference between $rose and posedge?
66. What is advantage of program block over clockcblock w.r.t race condition?
67. How to avoid the race condition between programblock ?
68. What is the difference between assumes and assert?
69. What is coverage driven verification?
70. What is layered architecture ?
71. What are the simulation phases in your verification environment?
72. How to pick a element which is in queue from random index?
73. What data structure is used to store data in your environment and why ?
74. What is casting? Explain about the various types of casting available in SV.
75. How to import all the items declared inside a package ?
76. Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL?
77. What is streaming operator and what is its use?
78. What are void functions ?
79. How to make sure that a function argument passed has ref is not changed by the function?
80. What is the use of "extern"?
81. What is the difference between initial block and final block?
82. How to check weather a handles is holding object or not ?
83. How to disable multiple threads which are spawned by fork...join
84 Why cannot initial statement be synthesizeable ?
85 Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?
86a What is the difference between blocking and nonblocking assignments ?
86 What is the difference between wire and reg data type ?
87 Write code for async reset D-Flip-Flop.
88 Write code for 2:1 MUX using different coding methods.
89 Write code for a parallel encoder and a priority encoder.
90 What is the difference between === and == ?
91 What is defparam used for ?
92 What is the difference between unary and logical operators ?
93 What is the difference between tasks and functions ?
94 What is the difference between transport and inertial delays ?
95 What is the difference between casex and case statements ?
96 What is the difference between $monitor and $display ?
97 What is the difference between compiled, interpreted, event based and cycle based simulators ?
98 What is code coverage and what are the different types of code coverage that one does ?
99 How will you handle multiple interfaces in UVM.
100 Explain APB and AHB using state machine
101 Explain Polymorphism and Inheritance using examples.
102When to use blocking and when to use non-blocking assignments.
103How do you control sequences in UVM {through testcase}.
1. Explain NAND flash operation
2. Diff btwn task & function
3. Types of arrays.
4. Advantage of dynamic array over associative array
5. Can you declare everything as associative array?
6. Explain packed and un packed array
7. Types of sequences
8. Explain ahb signals
9. Explain in details split and retry in hresp
10. Diff btwn @posedge and $rose
11. Uvm how driver and sequencer interact
12. How data passes from layer to layer in uvm
13. Diff btwn reg n wire
14. Diff between blocking n non blocking
15. Draw waveform for the code
Module ex;
Input [2:0] a;
Begin
a<= 3’b000;
a<=#5 3’b010;
a = #10 3’b101;
a<= #20 3’b111;
end
endmodule
16. How do you pass an array to a function.
17. About PREADY signal: is there a PREADY input to the slave
18. Without constraint, how will u generate random number between the range ‘x’ and ‘y’.
19. How to reduce the number of clock cycles taken for a transfer in APB/AHB protocol.. Eg: suppose a transfer takes 4 clock cycles, how can we make it in 3.
20. What does an ISR do. Suppose you have to write an isr, what all things you will write in that handler.
21. SIMULATOR related: when we compile any code, we give a filelist and the compiler compiles all the files in the list. Suppose some of the files is calling another file(`include option), then how will we compile that included file/directory
22. Basic verification approach: how will you verify an IP, in an SOC environment… how will you build the VC(approach).
23. Why sv over Verilog( explain properties of oops)
24. What is inheritance and polymorphism explain with example
25. Why/explain casting is used in terms of class and handles
26. Data types in sv
27. Randomization?
28. Cyclc randomization
29. How probability distribution is achived
Ex. 50% of time a =0
25% of time a = ( 1 - 1000)
25% of time a = (1001 – 2^32 - 1) how do you achieve this
30. Explain wait, randcase
31. Explain semaphore and mailboxes?
32. Mailboxes how does it work
33. Diff btwn mailbox and Que
34. Explain addr phase and data phase in AHB
35. Explain uvm flow
36. As soon as you get the spec how do you start verification
37. Why phases are required
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